Synchronization Primitives
Race Conditions
A race condition is "when the output of a process is unexpectedly dependent on timing or other events."
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We expected me to have $4,000 after both deposits. (Otherwise we are not observing the Law of the Conversation of Money, probably important to banks except during bailouts.)
Concurrency v. Atomicity
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Requires stopping or starting any thread at any time.
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Requires not stopping certain threads at certain times or not starting certain threads at certain times, i.e. providing some limited control to threads over their scheduling.
Critical Sections
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This set (or sets) of instructions will look atomic with respect to other threads executing code within the critical section.
void giveGWATheMoolah(account_t account, int largeAmount) {
int gwaHas = get_balance(account);
gwaHas = gwaHas + largeAmount;
put_balance(account, gwaHas);
notifyGWAThatHeIsRich(gwaHas);
return;
}
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What is local state private to each thread? gwaHas
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What is the shared state that is being accessed by giveGWATheMoolah? account
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What lines are in the critical section? 2-4
Critical Section Requirements
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Mutual Exclusion: this is the most basic property. Only one thread should be executing in the critical section at one time.
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Progress: all threads should eventually be able to proceed through the critical section.
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Performance: we want to keep critical sections as small as possible without sacrificing correctness.
Implementing Critical Sections
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Two possible approaches. Don’t stop, or don’t enter.
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On uniprocessors a single thread can prevent other threads from executing in a critical section by simply not being descheduled.
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In the kernel we can do this by masking interrupts. No timer, no scheduler, no stopping.
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In the multicore era this is only of historical interest. (This design pattern is usually broken.)
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More generally we need a way to force other threads—potentially running on other cores—not to enter the critical section while one thread is inside. How do we do this?
Atomic Instructions
Software synchronization primitives utilize special hardware instructions guaranteed to be atomic across all cores:
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Test-and-set: write a memory location and return its old value.
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Compare-and-swap: compare the contents of a memory location to a given value. If they are the same, set the variable to a new given value.
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Load-link and store-conditional: Load-link returns the value of a memory address, while the following store-conditional succeeds only if the value has not changed since the load-link.
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Many processors provide either test and set or compare and swap.
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On others equivalents can be implemented in software using other atomic hardware instructions.
Aside: Shared-Memory Multiprocessing
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As the number of cores on typical machines has continued to grow, some memory-based synchronization mechanisms have not scaled well.
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Building more scalable synchronization primitives for cache-coherent shared-memory machines is an open research problem.
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(The architecture of these machines itself is an open research problem.)
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The Bank Example: Test and Set
Let’s modify our earlier example to use a test and set:
Let’s try again:
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But what should I do if the
payGWA
is set?
The Bank Example: Test and Set
int payGWA = 0; // Shared variable for our test and set.
void giveGWATheMoolah(account_t account, int largeAmount) {
while (testAndSet(&payGWA, 1) == 1) {
; // Test it again!
}
int gwaHas = get_balance(account);
gwaHas = gwaHas + largeAmount;
put_balance(account, gwaHas);
testAndSet(&payGWA, 0); # Clear the test and set.
notifyGWAThatHeIsRich(gwaHas);
return;
}
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Busy waiting: threads wait for the critical section by "pounding on the door", executing the TAS repeatedly.
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Bad on a multicore system. Worse on a single core system! Busy waiting prevents the thread in the critical section from making progress!