Context Switching

CPU multiplexing: a historical perspective.

Preemption and context switching.

Potentially the most expensive and complex component of the system!

Multiple cores have emerged as a solution to thermal- and energy-management issues caused by transistor density.

But generally, even if you have more than one, there are fewer cores than tasks to be run.

It is way faster!

Faster than memory—usually addressed on the processor through out-of-order execution.

Way faster than disk—addressed by the operating system.

Way faster than you!—partially addressed by the operating system. (Nothing the operating system can really do about your limitations.)

15 ms "rule of thumb": 15,000,000 clock cycles!

40 ms based on 25 frames-per-second for "smooth" video: 40,000,000 clock cycles!

100 ms was the rule for old telephone systems, the delay point after which human conversation patterns start to break down: 100,000,000 clock cycles!

Long long ago, in a land before time, computers did not multitask. They did one thing at a time

That one thing had complete access to the machine in was running on.

The operating system—​if there was one—​was really just a library of routines to make programming easier. All abstractions, no multiplexing.

At some point more people wanted to use the computer. That was annoying, because the geeks didn’t have it all to themselves anymore, but they just told people to form a line.

At some point people wanted to interact with the computer, even multiple people interacting with the computer at the same time! Now what were the geeks to do?

They solved these problems by building operating systems. Scheduling evolved to meet the needs of computer users.

It is faster than other system components!

Inefficiency! Usage of slower parts of the system will cause the CPU to stall waiting for them to finish.

Operating systems emerged partly to hide delays caused by slow devices to keep the processor active.

Hiding processor delays requires only cooperative scheduling: threads only stop running when they require a long-latency operation.

Remember human perceptual limits?

The processors rapidly switches between tasks creating the notion of concurrency!

We refer to these transitions as context switches.

Timer interrupts generated by a timer device ensure that the operating system regains control of the system at regular intervals.

Timer interrupts are the basis of preemptive scheduling: the operating system doesn’t wait for the thread to stop running, instead it preempts it.

Rest of interrupt handling is unchanged.

Timer interrupts mean that a running thread may be stopped at any time.

When the thread restarts we want it to appear that nothing has happened, that execution was not interrupted.

How do we do this?

Registers

Stack

Saving thread state is the first thing that happens when the interrupt service routine is triggered. (Why?)

Saved state is sometimes known as a trap frame.

The kernel doesn’t trust (or want to pollute) the user thread’s stack.

Yes you can find that code. All the code is belong to you.

Exception return reloads the saved register state and then calls the MIPS instructions rfe, or return from exception.